Document Type : Original Research Paper


Computer Engineering Department, Science and Research Branch, Islamic Azad University,Tehran,Iran


Increasing the number of cores integrated on a chip and the problems of system on chips caused to emerge networks on chips. NoCs have features such as scalability and high performance. NoCs architecture provides communication infrastructure and in this way, the blocks were produced that their communication with each other made NoC. Due to increasing number of cores, the placement of the cores in NoC platform has become an important issue. If we
can map the application cores close to each other to place them with more communication requirements, the performance parameters will improve and the network will be more efficient. In
this paper, we propose two low complexity heuristic algorithms for the application mapping onto NoC to improve latency. In addition, one approach has been proposed to extract an Abstract graph from an application core graph, so, using this resent approach, we can map applications in two proposed algorithms. Moreover, we use bypass routers that can route packets in a cycle from the source to destination. Proposed algorithms and previous papers were compared on two real applications VOPD and MPEG-4 and results were reported.


Main Subjects

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