Computer Architecture and Digital Systems
Akram Reza; Parisa Jolani; Midia Reshadi
Volume 5, Issue 4 , November 2019, , Pages 205-212
Abstract
By increasing, the complexity of chips and the need to integrating more components into a chip has made network –on- chip known as an important infrastructure for network communications on the system, and is a good alternative to traditional ways and using the bus. By increasing the density of ...
Read More
By increasing, the complexity of chips and the need to integrating more components into a chip has made network –on- chip known as an important infrastructure for network communications on the system, and is a good alternative to traditional ways and using the bus. By increasing the density of chips, the possibility of failure in the chip network increases and providing correction and fault tolerance methods is one of the principles of today's chip design. Faults may have undesirable effects on the correct system operation and system performance. In this paper the communication infrastructure failure has been considered as same as link and router failure and the fault tolerance low cost routing algorithm has been suggested base on local fault information By using quad neighbor fault information to avoid back tracking in routing in order to select possible minimal path to destination. In this article, we have suggested cost aware fault tolerance (CAFT) routing algorithm. Our contribution in this algorithm is minimum local fault information, minimum routing decision overhead by implementing routing logic base and determining shortest possible path. For deadlock freedom using an additional virtual channel along Y dimension and prohibiting certain routing turns. In order to evaluate the performance of our routing, we compared it with other fault tolerant routing in terms of average packet latency, throughput and power.
Computer Networks and Distributed Systems
Midia Reshadi; Ali Ramezanzad; Akram Reza
Volume 4, Issue 2 , May 2018, , Pages 79-86
Abstract
Effective and congestion-aware routing is vital to the performance of network-on-chip. The efficient routing algorithm undoubtedly relies on the considered selection strategy. If the routing function returns a number of more than one permissible output ports, a selection function is exploited to choose ...
Read More
Effective and congestion-aware routing is vital to the performance of network-on-chip. The efficient routing algorithm undoubtedly relies on the considered selection strategy. If the routing function returns a number of more than one permissible output ports, a selection function is exploited to choose the best output port to reduce packets latency. In this paper, we introduce a new selection strategy that can be used in any adaptive routing algorithm. The intended selection function is named Modified-Neighbor-on-Path, the purpose of that is handling the condition of hesitation happening when the routing function provides a set of acceptable output ports. In fact, number of inquiries that each router has sent to its neighbors in determined past cycles is a new parameter that can be combined with number of free slots of adjacent nodes in the latest selection function named Neighbor-on-Path. Performance analysis is performed by using exact simulation tools under different traffic scenarios. Outcomes show how the proposed selection function applied to West-first and North-last routing algorithms outperforms in average delay up to 20 percent on maximum and an acceptable improvement in total energy consumption.