Computer Architecture and Digital Systems
Ali Ramezanzad; Midia Reshadi
Volume 4, Issue 2 , May 2018, , Pages 61-68
Abstract
Nowadays, the growing demand for supporting multiple applications causes to use multiple IPs onto the chip. In fact, finding truly scalable communication architecture will be a critical concern. To this end, the Networks-on-Chip (NoC) paradigm has emerged as a promising solution to on-chip communication ...
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Nowadays, the growing demand for supporting multiple applications causes to use multiple IPs onto the chip. In fact, finding truly scalable communication architecture will be a critical concern. To this end, the Networks-on-Chip (NoC) paradigm has emerged as a promising solution to on-chip communication challenges within the silicon-based electronics. Many of today’s NoC architectures are based on grid-like topologies which are also used in application-specific design.The small world network idea recently has been introduced in order to optimize the performance of the Networks-on-chip. Based on this method the architecture will be neither fully customized nor completely regular. Results have shown that by using the long-range links which optimized the network power and performance, the area consumption will exceed. We can derive from this that an acceptable bound on the area consumption should be considered. Based on the restriction of a designer, in this paper we want to present a methodology that will automatically optimize an architecture while at the same time considering the area consumption.
Computer Networks and Distributed Systems
Midia Reshadi; Ali Ramezanzad; Akram Reza
Volume 4, Issue 2 , May 2018, , Pages 79-86
Abstract
Effective and congestion-aware routing is vital to the performance of network-on-chip. The efficient routing algorithm undoubtedly relies on the considered selection strategy. If the routing function returns a number of more than one permissible output ports, a selection function is exploited to choose ...
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Effective and congestion-aware routing is vital to the performance of network-on-chip. The efficient routing algorithm undoubtedly relies on the considered selection strategy. If the routing function returns a number of more than one permissible output ports, a selection function is exploited to choose the best output port to reduce packets latency. In this paper, we introduce a new selection strategy that can be used in any adaptive routing algorithm. The intended selection function is named Modified-Neighbor-on-Path, the purpose of that is handling the condition of hesitation happening when the routing function provides a set of acceptable output ports. In fact, number of inquiries that each router has sent to its neighbors in determined past cycles is a new parameter that can be combined with number of free slots of adjacent nodes in the latest selection function named Neighbor-on-Path. Performance analysis is performed by using exact simulation tools under different traffic scenarios. Outcomes show how the proposed selection function applied to West-first and North-last routing algorithms outperforms in average delay up to 20 percent on maximum and an acceptable improvement in total energy consumption.