Document Type: Original Research Paper


Computer Engineering Department, Science and Research Branch, Islamic Azad University,Tehran,Iran


Increasing the number of cores integrated on a chip and the problems of system on chips caused to emerge networks on chips. NoCs have features such as scalability and high performance. NoCs architecture provides communication infrastructure and in this way, the blocks were produced that their communication with each other made NoC. Due to increasing number of cores, the placement of the cores in NoC platform has become an important issue. If we
can map the application cores close to each other to place them with more communication requirements, the performance parameters will improve and the network will be more efficient. In
this paper, we propose two low complexity heuristic algorithms for the application mapping onto NoC to improve latency. In addition, one approach has been proposed to extract an Abstract graph from an application core graph, so, using this resent approach, we can map applications in two proposed algorithms. Moreover, we use bypass routers that can route packets in a cycle from the source to destination. Proposed algorithms and previous papers were compared on two real applications VOPD and MPEG-4 and results were reported.


Main Subjects

[1] Santanu kundu, Santanu chattoadhyay, “Network-on-Chip:The Next Generation of System- on- Chip Integration”, London, CRC Press, 2015.
[2] pradip Kumar Sahu, Santanu Chattopadhyay, ”A survey on application mapping strategies for Network-on-Chip design, Elsevier, Journal of Systems Architecture, pp.60-76, 2013
[3] Axel Jantsch, Hannu Tenhunen, ”Networks on Chip”, United State of America, Kluwer Academic Publishers, 2003.
[4] Fernando Moraes, Ney Calazans, Aline Mello, Leandro Möller , Luciano Ost, “HERMES: an infrastructure for low area overhead packet switching network on chip”, Integration, the VLSI Journal, 2004, pp.69–93.
[5] Krishna T, Chia-Hsin Owen Chen, Woo Cheol Kwon, Li-Shiuan Peh, “Breaking the on-chip latency barrier using SMART”, IEEE 19th International Symposium on High performance Computer architecture, 2013.
[6] Amir Fadakar noghondar, Midia Reshadi, “A low-cost and latency bypass channel-based on chip network”, Springer, Journal of Super Computing, 2015.
[7] M.tavanpour, Ahmad Khademzadeh, Majid Janidarmian, “Chain-Mapping for mesh based Network-on-Chip architecture”, IEICE Electronics Express,pp.1535-1541,2009.
[8] Y.chen, Lunguo Xie, Jinwen Li, “An energy-aware heuristic constructive mapping algorithm for Network-on-Chip”, IEEE 8th International Conference on ASIC, pp.101-104, 2009.
[9] S.Tosun, “New heuristic algorithm for energy aware application mapping and routing on mesh-based NoCs”, Elsevier, Journal of system Architecture, pp.69-78, 2011.
[10] S.murali, G.demicheli, “Bandwidth Constrained mapping of cores onto NoC architectures, Proc. of design, Automation and test in Europe conference and exhibition, pp. 896-901, 2004.
[11] S.saeidi, Ahmad Khademzadeh, Fatemeh Vardi “Crinkle: a heuristic mapping algorithm for network on chip”, IEICE Electronics Express, pp.1737-1744, 2009.
[12] M.janidarmian, Ahmad Khademzadeh, Misagh Tavanpour, “Onyx: a new heuristic bandwidth-constrained mapping of cores onto network on chip”, IEICE Electronics Express, pp.1-7, 2009.
[13] A.Patooghy, Hamed Tabkhi, Seyed Ghassem Miremadi, “RMAP: a Reliability-Aware Application Mapping for Network-on- Chips”, 2010 third International conference on dependability, pp. 112-117, 2010.
[14] Partha Pratim Pande, Grecu.C, Jones.M, Ivanov.A, Saleh.R., “Performance Evaluation and Design Trade-Offs for Networkon- Chip Interconnect Architectures”, IEEE Transactions on Computers, pp.1225-1040, 2005.
[15] Xiaohang Wang, Mei Yang, Yingtao Jiang, Peng Liu, “Power-Aware Mapping for Network-on-Chip architectures under bandwidth and latency constraint”, International conference on embedded and multimedia computing, pp.1-6, 2009.