Document Type: Original Research Paper

Authors

1 Department of Computer Engineering Science and Research Branch, Islamic Azad University Tehran, Iran

2 Department of Computer Engineering Science and Research Branch, Islamic Azad University Tehran, Iran

Abstract

Nowadays, the growing demand for supporting multiple applications causes to use multiple IPs onto the chip. In fact, finding truly scalable communication architecture will be a critical concern. To this end, the Networks-on-Chip (NoC) paradigm has emerged as a promising solution to on-chip communication challenges within the silicon-based electronics. Many of today’s NoC architectures are based on grid-like topologies which are also used in application-specific design.The small world network idea recently has been introduced in order to optimize the performance of the Networks-on-chip. Based on this method the architecture will be neither fully customized nor completely regular. Results have shown that by using the long-range links which optimized the network power and performance, the area consumption will exceed. We can derive from this that an acceptable bound on the area consumption should be considered. Based on the restriction of a designer, in this paper we want to present a methodology that will automatically optimize an architecture while at the same time considering the area consumption.

Keywords

Main Subjects

1.    L. Benini and G. De Micheli, “Networks on chip: a new SoC paradigm,” IEEE Comput., vol 35, no.1 pp. 70-78, January. 2002.
2.    R. Marculescu, U.Y. Ogras, L.S. Peh, N. E. Jerger, and Y. Hoskote, “Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit perspectives”. J. IEEE TCAD, vol. 28, no. 1, pp.3-21, January, 2009.
3.    P. Vivet et al., "A $4 times 4 times 2$ Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links," in IEEE Journal of Solid-State Circuits, vol. 52, no. 1, pp. 33-49, Jan. 2017.
4.    B. Bohnenstiehl et al., "KiloCore: A 32-nm 1000-Processor Computational Array," in IEEE Journal of Solid-State Circuits, vol. 52, no. 4, pp. 891-902, April 2017. doi: 10.1109/JSSC.2016.2638459
5.    U.Y. Ogras, and R. Marculescu, ““It’s a Small World After All”: NoC Performance Optimization Via Long-Range Link Insertion”. Journal of IEEE TVLSI Systems, vol.14, no. 7, pp. 693-706, July, 2006.
6.    M. E. J. Newman and D. J.Watts, “Scaling and percolation in the smallworld network model,” Phys. Rev. E, vol. 60, pp. 7332–7342, 1999.
7.    D. J. Watts, Small Worlds, The Dynamics of Networks Between Order and Randomness, Princeton Univ. Press, New jersey, USA, 1999.
8.    A. Kahng, B. Li, L.-S. Peh, and K. Samadi. “Orion 2.0: A Fast and Accurate NoC Power and Area         Model for Early-Stage Design Space Exploration,” Proc. Design, Automation and Test in Europe (DATE), pp. 423–428, April, 2009.
9.    P. Meloni, I. Loi, F. Angiolini, S. Carta, M. Barbaro, and L. Raffo, “Area and power modeling for networks-on-chip with layout awareness,” J. VLSI Design, vol. 2007.
10.     M. Reshadi, A. Khademzadeh, and A. Reza, “Elixir: A New Bandwidth-Constrained Mapping for Networks- on- Chip,” will be appeared in IEICE Electronics Express.
11.    Princeton University, Orion 2.0 software release, Available: http://www.princeton.edu/~peh/orion.html
12.    Carnegie Mellon University, SLD: System Level Design Group, SmallNoC: Application-specific long-range link insertion tool, release 1.0, Available: http://www.ece.cmu.edu/~sld/software/SmallNoC.php
13.    Carnegie Mellon University, SLD: System Level Design Group, Worm_sim Simulator: a cycle accurate simulator for Networks-on-Chip, release 4.2, Available: http://www.ece.cmu.edu/~sld/software/worm_sim.php